The present invention relates to a clock timing extraction circuit which uses a phase control feedback loop to generate a clock synchronized with input data and also relates to an information recording/reproducing apparatus which uses the clock timing extraction circuit.
In a magnetic recording/reproducing apparatus for recording and reproducing an information signal in and from such a magnetic recording medium as a magnetic disk, for the purpose of identifying a data signal reproduced from the magnetic recording medium, it is necessary to generate a clock synchronized with the reproduced signal. A clock timing extraction circuit is used for this purpose and is arranged to generate a clock synchronized with the reproduced signal to cause the frequency and phase of the clock to follow variations in the frequency and phase of the reproduced information signal resulting from fluctuations in the rotation of the magnetic disk as the magnetic recording medium. Explanation will now be directed to a reproduction-associated signal processing circuit and a clock timing extraction circuit in the magnetic recording/reproducing apparatus as well as to a phase comparator in a phase locked loop (PLL) circuit constituting the clock timing extraction circuit, with reference to FIGS. 9, 10, 11 and 12.
Referring first to FIG. 9, there is shown a block diagram of an example of a reproduction-associated signal processing circuit for use in a general magnetic recording/reproducing apparatus to which the present invention can be applied. The illustrated signal processing circuit includes a magnetic recording medium 1, a magnetic head 2, a read/write amplifier 3, an automatic gain control (AGC) circuit 4, a filter circuit 5, an analog-to-digital (A-to-D) converter 6, a timing extraction circuit 7, a Viterbi decoder 8, a controller 9, and a microcomputer 10.
In the drawing, an information signal recorded on the magnetic recording medium 1 is reproduced by the magnetic head 2 into an electric signal 101 that is then amplified by the read/write amplifier 3 to obtain an amplified analog signal 102. The amplified analog signal 102 is subjected at the AGC circuit 4 to a controlling operation with respect to its amplitude value to generate an output signal 103. The signal 103 is then subjected at the filter circuit 5 to a waveform processing operation to improve the performance of the Viterbi decoder 8. The filter circuit 5 outputs a reproduction signal 104 subjected to the waveform processing operation and sends it to the A-to-D converter 6 to be quantized. The A-to-D converter 6 outputs a reproduction data signal 105 subjected to the quantizing operation. The data signal 105 is sent to the AGC circuit 4 and the Viterbi decoder 8 and also sent to the timing extraction circuit 7 which generates a timing clock 106 necessary for data identification. The Viterbi decoder 8 decodes the reproduction data signal 105 received from the A-to-D converter 6 on the basis of the timing clock 106 received from the timing extraction circuit 7. The Viterbi decoder 8 outputs a decoded reproduction data signal 107 and a timing clock 108 and supplies them to the controller 9. The controller 9, under control of the microcomputer 10, subjects the input reproduction data signal 107 to a format converting operation and transmits it to a host device (not shown).
In this connection, the timing clock 106 issued from the timing extraction circuit 7 is also used as a sampling clock of the A-to-D converter 6 and as a timing clock of the AGC circuit 4. The filter circuit 5 is made up of an equalizer 5a for performing Nyquist equalizing operation over the input signal 103 and (1+D) block 5b for performing partial response class 4 (PR4) operation, as shown in FIG. 10. While the filter circuit is placed at the former stage of the A-to-D converter in FIG. 9, it can be replaced at the latter stage of the A-to-D converter. In this case, the filter circuit is included in the feedback loop for the clock timing extraction.
With such a reproduction-associated signal processing circuit as shown in FIG. 9, when it is desired to use a Viterbi decoder as a decoder 8 into which a digital value is input, it is desirable from the viewpoint of its performance that the AGC circuit 4 and timing extraction circuit 7 use the digital value of the input data 105.
FIG. 11 is a block diagram of the timing extraction circuit 7 of a conventional digital control (analog drive) type, which includes a phase comparator 11, a digital-to-analog (D-to-A) converter 12, a loop filter 13, a voltage controlled oscillator (VCO) 14. Elements in FIG. 11 which correspond to those in FIG. 9 are denoted by the same reference numerals.
In the drawing, the VCO 14 generates the aforementioned timing clock 106. The reproduction data signal 105 received from the A-to-D converter 6 is subjected, at the phase comparator 11, to a detection of a phase difference from the timing clock 106. A digital value 110 indicative of the phase difference received from the phase comparator 11 is converted, at the D-to-A converter 12, to an analog value 111 that is then subjected at the loop filter 13 to an integrating operation to obtain a control voltage 112. Since the oscillation frequency of the VCO 14 is controlled according to the control voltage 112, the VCO 14 outputs a timing clock 106 that is synchronized in frequency and phase with the input data 105.
Turning now to FIG. 12, there is shown a block diagram of an example of the phase comparator 11 in FIG. 11 which includes a discriminator (or a quantizer) 21, delays 22, 23, multipliers 24, 25, and a subtracter 26.
This phase comparator is designed to calculate a phase error on the basis of an amplitude value at a sample point as described in a paper written by Kurt H. Mueller, et al. and entitled "Timing Recovery in Digital Synchronous Data Receivers" in IEEE Transactions on Communications, May, 1976.
In FIG. 12, the reproduction data 105 received from the A-to-D converter 6 (see FIG. 11) is subjected at the discriminator 21 to its level ("1" or "0") judging operation, and the discriminator 21 generates a decision signal 201 indicative of its result. The reproduction data signal 105 and the decision signal 201 are subjected at their respective delays 22 and 23 to a delay corresponding to one sample. The multiplier 24 multiplies a reproduction data signal 202 received one-sample earlier from the delay 22 by the decision signal 201 from the discriminator 21; while the multiplier 25 multiplies a decision signal 23 received one-sample earlier from the delay 23 by the reproduction data signal 105. An output data signal 204 of the multiplier 24 is subtracted by the subtracter 26 from an output data signal 205 of the multiplier 25 to thereby obtain the aforementioned phase difference 110.
Explanation will next be made as to the waveforms of signals at various points during the magnetic recording/reproducing operation and as to the operation of the phase comparator 11 based thereon.
FIG. 13 shows how a series of codes (a.sub.k) taking a binary value of "0" or "1" to be recorded is converted into a signal x(t) to be inputted to the A-to-D converter 6 through a path including a precoder 15, a read amplifier 3a, the magnetic disk 1, a write amplifier 3b, and an equalizer 5a and a (1+D) block 5b of the filter 5. In this case, since the AGC circuit 4 has no effect on the transmission characteristics, it is omitted.
In FIG. 13, the record-associated precoder 15 precoded the code signal a.sub.k and outputs a precode output signal b.sub.k. In the illustrated example, a characteristic 1/(1-D.sup.2) is provided for the code signal a.sub.k. In this connection, reference symbol D refers to a delay operator which delays an input signal by a bit period T. Since an isolated pulse exhibits a differentiating characteristic in a reproduction mode, the equalizer 5a offers Nyquist equalization to provide the (1-D) characteristic. Furthermore, the latter stage performs the (1+D) operation to offer the overall (1-D.sup.2) transmission characteristic.
The output signal x(t) is expressed by the following equation (1). ##EQU1## where h(t)=sin(.pi.t/T)/(.pi.t/T)
Assume that c.sub.k is written as follows. EQU c.sub.k =(b.sub.k -b.sub.k-2) (2)
Then, the following relation is satisfied. EQU c.sub.k .epsilon.{-1,0,1}
Further, when t=0, i.e., when a phase error between the reproduced data signal and the clock is zero, h.sub.-k (t) is: ##EQU2##
Thus, the decision conditions of the discriminator 21 in the phase comparator should be defined as follows in order to produce an estimate {c.sub.k }for the c.sub.k from a value x.sub.k (.tau.) at a time point t (=.tau.+kT) where a phase error .tau. is present. ##EQU3##
The phase comparator 11, on the basis of the {c.sub.k } and x.sub.k (.tau.), generates an output signal y.sub.k (.tau.) which follows at a point in time (.tau.+kT ). ##EQU4##
When the estimate c.sub.k is equal to c.sub.k, the following relationship is satisfied. ##EQU5##
Since h.sub.n (.tau.).apprxeq.0 when a relationship of .vertline.n.vertline..ltoreq.2 is satisfied, the following equation is satisfied. EQU y.sub.k (.tau.)=A.sub.-1 h.sub.-1 (.tau.)+A.sub.1 h.sub.1 (.tau.)(8)
where A.sub.-1 =c.sub.k.sup.2 -c.sub.k-1 c.sub.k+1 EQU A.sub.1 =c.sub.k c.sub.k-2 -c.sub.k-1.sup.2
Assuming now that the values of the A.sub.-1 and A.sub.1 are fully random, though they actually vary with the array of the code sequence {a.sub.k }, then averages E(A.sub.-1) and E(A.sub.1) for the values A.sub.-1 and A.sub.1 meet the following relationship. EQU E(A.sub.-1)=-E(A.sub.1)=A(.noteq.0) (9)
Hence, the following equation is satisfied. EQU y.sub.k (.tau.)=A{h.sub.-1 (.tau.)-h.sub.t (.tau.)}tm (10)
For an input data signal having a phase error .tau., the phase comparator 11 generates an output signal y.sub.k (.tau.) as mentioned above. Since the phase comparator 11 has a phase comparison characteristic that is substantially linear to the phase error .tau., the timing extraction circuit 7 performs its phase feedback control operation on the basis of the digital value inputted to the decoder 8 to generate a timing clock synchronous with the input data signal.
The timing extraction circuit 7 performs its feedback control operation based on the PLL circuit including the A-to-D converter, and included in its closed loop are the A-to-D converter 6, phase comparator 11 and D-to-A converter 12 connected in series, as already mentioned above. Shown in FIG. 14 is a timing chart for explaining a sequence of the operation of the A-to-D converter 6, phase comparator 11 and D-to-A converter 12. Problems in the prior art technique will be explained with use of FIG. 14.
The A-to-D converter 6 takes the analog input signal 104 at the timing of an rising edge in the timing clock 106 received from the timing extraction circuit 7, compares the value of the input signal with a reference voltage set therein, and encodes its comparison result into the binary data (digital value) signal 105. Reference symbol t.sub.1 in FIG. 14 denotes a time between the take-in at the rising edge and the establishment of the output signal 105.
The phase comparator 11 accepts the output data signal 105 of the A-to-D converter 6, processes it therein, and outputs the digital value signal 110 having phase error information. This digital-value calculation time for the phase comparator 11 is assumed to be t.sub.2. The D-to-A converter 12 latches the output data signal 110 of the phase comparator 11 at the timing of a rising or falling edge in the timing clock 106, converts it into the analog value signal 111, and outputs it. This edge of the timing clock 106 at which timing the output data signal 110 of the phase comparator 11 is accepted, corresponds to one edge of the timing clock after a time t.sub.0 elapses from the rising edge of acceptance of the analog signal at the timing extraction circuit 7. The time t.sub.0 corresponds to a sum of the aforementioned time t.sub.1, a time t.sub.2 and a setup time t.sub.3 necessary for the latch. Accordingly, a time duration after the A-to-D converter 6 accepts the data signal 104 until the D-to-A converter 12 outputs the analog value signal 111 having the phase error information must include at least a delay time of 0.5 T (corresponding to a phase difference of 180 degrees), where T denotes one period of the clock.
When the frequency of the timing clock 106 becomes high and its period T becomes relatively small with respect to the t.sub.0 uniquely determined by its circuit scale, process, etc., the aforementioned delay time 0.5 T is required to be greater. This also applies to the calculation time including arithmetic pipeline to calculate the phase error at the phase comparator. These time lags undesirably affect the feedback control as a waste time. When a secondary PLL circuit is employed for this feedback control for example, a waste time element nT and a phase margin .phi..sub.m in the loop have a relationship which follows. ##EQU6## where, .xi. denotes a damping factor, .omega..sub.n denotes a natural angular frequency, .omega..sub.s denotes a sample angular frequency and satisfies a relationship .omega..sub.s ={2.pi./T}.
In the absence of the waste time (n=0), the phase margin .phi..sub.m is expressed as a function of .xi. alone; whereas, in the presence of the waste time, the phase margin .phi..sub.m is expressed as a function of .xi., n and .omega..sub.n /.omega..sub.s and thus the phase margin is decreased with the increase of n and .omega..sub.n /.omega..sub.s. Since a certain level of phase margin .phi..sub.m must be secured in order to obtain a stable response, determination of the waste time based on the circuit arrangement, etc. automatically determines an upper limit value of .omega..sub.n /.omega..sub.s.
FIG. 15 shows a phase acquisition characteristic of the PLL circuit, in which the abscissa denotes normalization of multiplication of time t by the natural angular frequency .omega..sub.n and the ordinate denotes normalization of division of the phase error .phi.(t) by the initial phase error .phi..sub.0. The shape of this response is uniquely determined for each value Of the damping factor .xi..
When it is prescribed that phase acquisition is completed when the absolute value .vertline..phi.(t).vertline. of a phase error becomes below a certain phase error .phi..sub.1 and at a time when the completion of the phase acquisition in the PLL circuit corresponds to an acquisition time T.sub.aq ; the acquisition time T.sub.aq can be expressed as a function of the natural angular frequency .omega..sub.n and the initial phase error .phi..sub.0. That is, the smaller the natural frequency .omega..sub.n and the greater the initial phase error .phi..sub.0, the larger the acquisition is. Upon reading of data from a magnetic disk unit or the like, a time T.sub.sync, within which the phase acquisition of a timing extraction circuit using the PLL circuit must be completed, is determined by the format (PLO sync duration) of the disk and by a data transmission rate thereof. Therefore, the natural frequency .omega..sub.n is set so that the acquisition time T.sub.aq is smaller than the time T.sub.sync.
When consideration is paid to the stability of the response as mentioned above, however, the natural frequency .omega..sub.n is determined by its upper limit value and thus the acquisition time T.sub.aq is also limited in its minimum value. This results in a problem that the transmission rate cannot be set to be higher than a certain constant value. On the contrary, when the natural angular frequency .omega..sub.n is set so that the acquisition is completed within the time T.sub.sync corresponding to the transmission rate, the phase margin .phi..sub.m is decreased and therefore the response becomes undesirably unstable.